1. VLSI Implementation of an adaptive Edge Enhanced color interpolation Processor for Real-Time Video Applications

2. Demonstrating HW-SW Transient Error Mitigation on the single-chip cloud computer data plane

3. Enhanced Memory reliability against multiple cell upsets using Decimal Matrix code

4. Wear out Resilience in NOCs through an Aging Aware Adaptive Routing Algorithm

5. High-Performance H.264/AVC Intra-Prediction Architecture for Ultra High Definition Video Applications On-Chip Memory Hierarchy in one Coarse-Grained Reconfigurable Architecture to compress memory space and to reduce time

6. A Voltage based Leakage current calculation scheme and its application to Nanoscale and FinFET Standard cell designs

7. High Throughput and Low complexity BCH decoding Architecture for Solid-State Drives

8. Nonbinary LDPC Decoder based on Simplified Enhanced Generalized Bit-Flipping Algorithm

9. A 2-D Interpolation based ORD Processor with Partial Layer Mapping for MIMO-OFDM Systems

10.Digitally controlled Pulse Width Modulator for On-Chip Power Management

11. UNION: A Unified Inter/Intrachip Optical Network for Chip Multiprocessors

12. High-Throughput Multistandard Transform Core supporting MPEG/H.264/VC-1 using Common Shared Distributed Arithmetic

13. Alogirthm and Architecture for a Low-Power Content Addressable Memory based on Sparse Clustered Networks

14. A Variation-Aware Preferential Design approach for Memory- Based Reconfigurable Computing

15. Asynchronous Domino Logic Pipeline Design Based on Constructed Critical data path

16. Low-Power Digital Signal Processor Architecture for Wireless Sensor Nodes

17. Application Mapping Onto Mesh-Based Network-On-Chip using Discrete Particle Swarm Optimization

18. Novel Reconfigurable Hardware Architecture for Polynomial Matrix Multiplications

19. Single-Bit Pseudo Parallel Processing Low-oversampling Delta-Sigma Modulator suitable for SDR Wireless Transmitters

20. A Lattice Reduction Aided MIMO Channel Equalizer in 90 nm CMOS achieving 720 Mb/s

21. Low Power, Minimally Invasive Process Compensation Technique for Sub-Micron CMOS Amplifiers

22. Low-Energy Two-stage Algorithm for High Efficiency Epileptic Seizure Detection

23. An Ultralow Power Multirate FSK Demodulator for High-Speed Biomedical Zero-IF Receivers

24. Ultra-High Throughput Low-Power Packet Classification

25. Level-Converting Retention Flip-Flop for Reducing Standby Power in ZigBee SOC's

26. Area-Delay-Power Efficient Fixed-point LMS Adaptive filter with low adaptation delay

27. Energy Efficiency Optimization through codesign of the Transmitter and Receiver in High-speed On-Chip Interconnects

28. A Fast application based supply voltage optimization method for dual voltage FPGA

29. Reliable Low-Power Multiplier Design using Fixed-Width Replica Redundancy block

30. Low-Power Pulse-Triggered Flip-Flop Design based on a signal feed-through

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